To achieve feature sizes that are smaller than the lithographic ground rule, a process known as resist trimming is used. For example, to achieve transistor gate length smaller than ground rule, the patterned resist mask can be trimmed to reduce the critical dimension (CD) of the polysilicon line to the target dimension. However, conventional resist trimming processes cause the polysilicon line end to pull back much more than do its sides.
The distance by which the photoresist line ends is shortened as compared to the reduction in line width is referred to as the line end shortening (LES) ratio. The LES ratio is typically >1.5 to 2. However, such a high LES ratio is not tolerable for some devices, such as SRAM ICs, particularly in light of shrinking device dimensions coupled with increased density. As shown in FIGS. 1-2, high LES ratio can result in transistor leakage. FIG. 1 shows a portion of a substrate of an IC 100. Line end pull back can result in the ends of polysilicon gates 210, 212 of adjacent transistors 220, 222 (as shown in FIG. 2) to fall on an active region 240 of the substrate at location A, instead of on the field region 260. This results in current leakage, as represented by the dotted line in FIG. 1, between the transistors.
To reduce LES, the use of a silicon nitride or silicon oxynitride hard mask to pattern polysilicon gates has been proposed. Hard mask processes, however, besides contributing to higher costs and lower product yields, may be incompatible with some processes. For example, removal of the hard mask after etching is completed may cause erosion of a silicon nitride liner used in shallow trench isolations (STIs) due to lack of etch selectivity, forming divots at the edges of the STIs. This can lead to device leakage, impacting performance and reliability. Additionally, the use of hard masks increases cost as well as making defect control more difficult.